Spin qubits in semiconductor structures bring the promise of large-scale 2D integration, with the possibility to incorporate the control electronics on the same chip. Recent spin-qubit experiments demonstrate gate operations and readout well within 1% error rate. This error rate, based on the error threshold of the surface code under circuit-level noise, has become a standard figure of merit for gate errors in the spin-qubit community. The isotropic circuit-level noise model, however, assumes that gate errors, measurement errors, and data qubit errors during ancilla measurements occur with the same probability suggesting that the requirements might be less stringent for some of these ingredients. Furthermore, recent developments in quantum error correction codes present opportunities to improve the error threshold and reduce connectivity requirements compared to Kitaev’s surface code. In this work we consider state-of-the-art error-correction codes that require only nearest-neighbour two-qubit gates, and study their performance under anisotropic circuit-level noise that accounts for distinct error rates for gates, measurement and qubit decoherence during idling. We present the spin-qubit layout required for each of the error correction codes, accounting for additional elements required by spin-qubit architectures such as auxiliary quantum dots for spin-blockade-assisted readout.